Desenvolvimento de estruturas paralelas em FPGA e implementação de controladores digitais para aplicação em filtros ativos de potência

Abstract

This paper presents a parallel approach to FPGA implementation of digital controllers, in order to reduce the computational time for implementing the control laws. The control technique used in the proposed implementation can be applied for selective harmonic compensation in active power filters (APF). To compensate for even a small number of harmonics requires multiple calculation instructions involving multiplications and additions. Thus, to improve the performance of the computer system is proposed to implement a parallel structure of the controller. To compensate for a larger number of harmonics is performed in the decomposition voltages of the harmonic components into their frames synchronous using the Discrete Fourier Transform. This strategy allows a calculation time fixed regardless of the number of harmonics up to the limit imposed by the sampling frequency. The experimental results are presented to compare the runtime of the proposed parallel approach with the sequential execution time conventionally used in the literature.