Simulador web de arquiteturas baseadas no processador neander: uma ferramenta de apoio ao ensino de arquitetura e organização de computadores

Abstract

Teaching Computer Architecture presents significant challenges in technology courses due to the abstract nature of how hardware works and the requirement to understand the internal operations of processors. In this context, the use of simulators has become an effective pedagogical strategy to bridge the gap between theory and practice. This work presents the development of a web-based simulator for the Neander didactic processor, aimed at supporting the teaching-learning process of this architecture. The developed tool features a modular architecture and offers essential functionalities, such as an assembly language code editor, local file persistence mechanisms, and both step-by-step and full program execution modes. The system enables detailed visualization of the final state of memory and registers after processing, facilitating the understanding of instruction effects on the hardware. As a result, this work delivers an accessible tool focused on execution accuracy, reducing the distance between theoretical concepts and practical experimentation in introductory computing courses.