Proposição do paradigma orientado a notificações no desenvolvimento de circuitos lógico-digitais reconfiguráveis

Abstract

Usual computer architectures have shown issues in following the growing demand for processing. The FPGAs are an interesting alternative to these architectures, especially for applications that require considerable processing power and execution parallelism. Even with promising features, the use of FPGAs is complicated by its programming model and by the traditional hardware synthesis languages, which demands great technical knowledge. Alternatively, an easier way to enjoy the potential of FPGAs is using high-level synthesis tools. These tools make easier the FPGAs programming, however usually the generated circuits demand more resources, are slower, and exploit less parallelism than circuits described using traditional hardware synthesis languages. A solution to some of this problems is shown in the Notification Oriented Paradigm (NOP). The NOP presents features of avoiding redundancies and provide fine decoupling of parts of the code, which enables parallelization and even distribution, something particularly interesting for digital hardware synthesis. This is done through logical-causal and factual-executional entities that collaborate by means of punctual notifications. In addition, they emerge from high-level rule-oriented programming. Moreover, there are a framework and language for NOP software. That said, this work presents an implementation of NOP where all elements of this paradigm are modeled in reconfigurable logic blocks, using VHDL language. This new solution of NOP for digital hardware, called the PON-HD 1.0, was developed to facilitate the synthesis for FPGA. With the PON-HD 1.0 you can generate VHDL code for FPGA directly from a NOP program written in high-level language. This language and its compiler are called LingPON-HD 1.0, also proposed as part of this work and inspired by the previous language of NOP for software. In order to evaluate the performance and stability of circuits generated with the technology of PON-HD 1.0, some comparative experiments were carried out with traditional hardware synthesis languages. These experiments have shown that the technology of PON-HD 1.0 allows to create, with considerable speed and ease, trusted digital circuits with appropriate performance and parallelism, based on the performed comparisons. In conclusion, the results demonstrate the feasibility of the NOP as a paradigm and toolchain for suitable development in FPGAs scope.