Implementação do algoritmo Radix-2 para cálculo da FFT em FPGA

Abstract

The objective of this work is the development of a specific hardware for the calculation of Fast Fourier Transform (FFT), based on the implementation of the Radix-2 algorithm in FPGA, using parallelism to increase the computational efficiency. This work introduce the main concepts about FFT, the Radix-2 algorithm, the CORDIC algorithm, and the project of parameters that maximize the performance of these algorithms. The device chosen for FFT implementation is the ZynqBerry - TE0726, which has an FPGA of the Zynq-700 family.0. Two FFT architectures are implemented in this work; the first FFT has 16 points, and is computed with only 12 cycles of textit clock, achieving a SQNR performance of 52dB. The second FFT has 1024 points, and is computed with 1728 clock cycles, achieving a SQNR performance of 41dB. At the end it is possible to understand how an FFT is designed and implemented in an advantageous environment such as the FPGA.