Desenvolvimento e comparação de circuitos integrados que constituem uma malha de captura de fase

Abstract

The focus of this project was to study and develop several integrated circuits that compose a PLL, utilizing a linearized model, with equations relevant to the study of a closed loop system. The integrated circuits were developed with the help from the auxiliary software DSCH, that can create them from a Verilog script. During the development period was established a voltage controlled oscillator using the current starved method in the integrated circuits topology, where I was possible to obtain two operation circuits, one developed by the software DSCH and another manually, obtaining the maximum frequency of 9.76GHz and 8.67GHz respectively. The phase detector created was developed using the XOR topology, where a reducing topology of the number of transistors and area was applied. The software DSCH also developed a XOR with good results considering the reduction of transistors used. Finally, after the schematization and test of each block operating individually, it was possible to develop integrated circuits acting as a PLL, with a basis on the studied methodology, both circuits were applied an entry signal with a frequency of 4GHz and an amplitude of 0.6V, with that, after an efficiency study was made, it was possible to notice that the manually developed circuits was more efficient than the circuit developed by the software DSCH.