Arquitetura paralela reconfigurável baseada em fluxo de dados implementada em FPGA

Abstract

Many real-world engineering problems require high computational power, especially concerning to the processing speed. Modern parallel processing techniques play an important role in reducing the processing time as a consequence of the parallel execution of machinelevel operations for a given application software , taking advantage of possible independence between data and operations during processing time. Recently, reconfigurable computation has gained large attention thanks to its ability to combine hardware performance and software flexibility, allowed the developmentof very complex, compact and powerful systems for custom application. Tjis work proposes a new architecturefor parallel reconfigurable computation that associate the power of parallel processing and the flexibility of reconfigurable devices. This architecture allows quick customization of the system for many problems and, particularly, for numerical computation. For instance, this architecture can exploit the inherent parallelism of the numerical computation of differential equations, where several operations can be executed at the same time using a dataflow graph model of the problem. The proposedarchitecture is composed by a Control Unit , responsible for the control of all Processing Elements (PEs) and the data flow between them; and many application-customized PEs, responsible for the executionof operations. Diferrently from sequential computation, the parallel computation takes advantageof the available PEs and theirspecificity for the aplication. Therefore, the proposed architecture can offerhigh performance, scalability and customized solutions for engineering problems.